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september 2003 this document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. future routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with "am" and "mbm". to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. tm tm tm spansion mcp data sheet tm
ds05-50230-2e fujitsu semiconductor data sheet stacked mcp (multi-chip package) flash memory & sram cmos 32m ( 16) flash memory & 4m ( 16) static ram mb84vd22184fm -70 /mb84vd22194fm -70 n features ? power supply voltage of 2.7 v to 3.1 v ? high performance 70 ns maximum access time (flash) 70 ns maximum access time (sram) ? operating temperature C30 c to +85 c ? package 56-ball fbga (continued) n product line up note: both v cc f and v cc s must be in recommended operation range when either part is being accessed. n pac k ag e part no. vd22184fm / vd22194fm supply voltage(v) v cc f= 3.0v v cc s= 3.0v max address access time (ns) 70 70 max ce access time (ns) 70 70 max oe access time (ns) 30 35 56-ball plastic fbga (bga-56p-m03) +0.1 v C0.3 v +0.1 v C0.3 v
mb84vd22184fm/vd22194fm -70 2 (continued) flash memory ? simultaneous read/write operations (dual bank) bank 1 : 8 mbit (8 kb 8 and 64 kb 15) bank 2 : 24 mbit (64 kb 48) host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations. read-while-erase read-while-program ? minimum 100,000 write/erase cycles ? sector erase architecture eight 4k word and sixty-three 32k word sectors in word mode any combination of sectors can be concurrently erased. also supports full chip erase. ? boot code sector architecture mb84vd22184: top sector mb84vd22194: bottom sector ? embedded erase tm * algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm * algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready-busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode. ?low v cc f write inhibit 2.5 v ? hiddenrom region 256 byte of hiddenrom, accessible through a new hiddenrom enable command sequence factory serialized and protected to provide a secure electronic serial number (esn) ?wp /acc input pin at v il , allows protection of outermost 2 8 bytes on boot sectors, regardless of sector protection/unprotection status. at v ih , allows removal of boot sector protection at v acc , increases program performance ? erase suspend/resume suspends the erase operation to allow a read in another sector within the same device ? please refer to mbm29dl34tf/bf datasheet in detailed function sram ? power dissipation operating : 40 ma max standby : 10 m a max ? power down features using ce1 s and ce2s ? data retention supply voltage: 1.5 v to 3.1 v ?ce1 s and ce2s chip select ? byte data control: lb (dq 7 to dq 0 ), ub (dq 15 to dq 8 ) *: embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
mb84vd22184fm/vd22194fm -70 3 n pin assignment (bga-56p-m03) (top view) marking side c7 a 13 c6 a 9 c5 a20 c4 ry/by c3 a 18 c2 a 5 c1 a 2 c8 n.c. e7 n.c. e6 dq 6 e3 dq 1 e2 v ss e1 a 0 e8 a 16 f7 dq 15 f6 dq 13 f5 dq 4 f4 dq 3 f3 dq 9 f2 oe f1 cef f8 n.c. d7 a 14 d6 a 10 d3 a 17 d2 a 4 d1 a 1 d8 n.c. g7 dq 7 g6 dq 12 g5 vccs g4 vccf g3 dq 10 g2 dq 0 g1 ce1s g8 vss h7 dq 14 h6 dq 5 h5 n.c. h4 dq 11 h3 dq 2 h2 dq 8 b7 a 12 b6 a 19 b5 ce2s b4 reset b3 ub b2 a 6 b1 a 3 b8 a 15 a7 a 11 a6 a 8 a5 we a4 wp/acc a3 lb a2 a 7
mb84vd22184fm/vd22194fm -70 4 n pin description pin name function input/output a 17 to a 0 address inputs (common) i a 20 to a 18 address inputs (flash) i dq 15 to dq 0 data inputs / outputs (common) i/o ce f chip enable (flash) i ce1 s chip enable (sram) i ce2s chip enable (sram) i oe output enable (common) i we write enable (common) i ry/by ready/busy outputs (flash) open drain output o ub upper byte control (sram) i lb lower byte control (sram) i reset hardware reset pin / sector protection unlock (flash) i wp /acc write protect / acceleration (flash) i n.c. no internal connection v ss device ground (common) power v cc f device power supply (flash) power v cc s device power supply (sram) power
mb84vd22184fm/vd22194fm -70 5 n block diagram v ss v cc s 32 m bit reset flash memory we 4 m bit static ram ce f a 20 to a 0 oe ce1 s v ss v cc f a 20 to a 0 a 17 to a 0 dq 15 to dq 0 ry/by lb ub wp /acc ce2s dq 15 to dq 0 dq 15 to dq 0
mb84vd22184fm/vd22194fm -70 6 n device bus operations ? user bus operations legend: l = v il , h = v ih , x = v il or v ih . see dc characteristics for voltage levels. *1 : other operations except for indicated this column are inhibited. *2 : we can be v il if oe is v il , oe at v ih initiates the write operations. *3 : do not apply ce f = v il , ce1 s = v il and ce2s = v ih at a time. *4 : it is also used for the extended sector group protections. *5 : wp /acc = v il ; protection of boot sectors. wp /acc = v ih ; removal of boot sectors protection. wp /acc = v acc (9v) ; program time will reduce by 40%. operation * 1, * 3 ce fce1 sce2s oe we lb ub dq 7 to dq 0 dq 15 to dq 8 reset wp / acc * 5 full standby h hx x x x x high-z high-z h x xl output disable hl h h h x x high-z high-z hx x x h h high-z high-z l hx h h x x high-z high-z xl read from flash * 2 l hx lhxx d out d out hx xl write to flash l hx hlxx d in d in hx xl read from sram h l h l h ll d out d out hx h l high-z d out lh d out high-z write to sram h l h x l ll d in d in hx h l high-z d in lh d in high-z temporary sector group unprotection* 4 xx xxxxx x x v id x flash hardware reset x hx x x x x high-z high-z l x xl boot block sector write protection xx xxxxx x x x l
mb84vd22184fm/vd22194fm -70 7 n absolute maximum ratings *1 : minimum dc voltage on input or i/o pins is C0.3 v. during voltage transitions, input or i/o pins may undershoot v ss to C1.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc f+0.3 v or v cc s+0.4 v. during voltage transitions, input or i/o pins may overshoot to v cc f+1.0 v or v cc s + 1.0 v for periods of up to 20 ns. *2 : minimum dc input voltage on reset pin is C0.5 v. during voltage transitions, reset pins may undershoot v ss to C2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in -v cc f or v cc s) does not exceed + 9.0 v. maximum dc input voltage on reset pins is +13.0 v which may overshoot to +14.0 v for periods of up to 20 ns. *3 : minimum dc input voltage on wp /acc pin is C0.5 v. during voltage transitions, wp /acc pin may undershoot vss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is +10.5 v which may overshoot to +12.0 v for periods of up to 20 ns, when v cc f is applied. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions note: operating ranges define those limits between which the functionality of the device is guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. parameter symbol rating unit min max storage temperature tstg C55 +125 c ambient temperature with power applied t a C30 +85 c voltage with respect to ground all pins except reset , wp /acc * 1 v in , v out C0.3 v cc f + 0.3 v v cc s + 0.4 v v cc f/v cc s supply * 1 v cc f, v cc s C0.3 +3.3 v reset * 2 v in C0.5 +13.0 v wp /acc * 3 v in C0.5 +10.5 v parameter symbol value unit min max ambient temperature t a C30 +85 c v cc f/v cc s supply voltages vccf, vccs +2.7 +3.1 v
mb84vd22184fm/vd22194fm -70 8 n electrical characteristics 1. dc characteristics (continued) parameter symbol test conditions value unit min typ max input leakage current i li v in = v ss to v cc f, v cc s C1.0 +1.0 m a output leakage current i lo v out = v ss to v cc f, v cc s C1.0 +1.0 m a reset inputs leakage current i lit v cc f = v cc f max, v cc s = v cc s max, reset = 12.5v 35 a flash v cc active current (read) * 1 i cc1 f ce f = v il , oe = v ih t cycle = 5 mhz 18 ma t cycle = 1 mhz 4 ma flash v cc active current (program/erase) * 2 i cc2 f ce f = v il , oe = v ih 30ma flash v cc active current (read-while-program) * 5 i cc3 fce f = v il , oe = v ih 48ma flash v cc active current (read-while-erase) * 5 i cc4 fce f = v il , oe = v ih 48ma flash v cc active current (erase-suspend-program) i cc5 fce f = v il , oe = v ih 35ma acc input leakage current i lia v cc f = v cc f max, v cc s = v cc s max, wp /acc = v acc max 20ma sram v cc active current i cc1 s v cc s = v cc s max, ce1 s = v il , ce2s = v ih t cycle =10 mhz 40 ma sram v cc active current i cc2 s ce1 s = 0.2 v, ce2s = v cc s C 0.2 v t cycle = 10 mhz 40 ma t cycle = 1 mhz 8 ma flash v cc standby current i sb1 f v cc f = v cc f max, ce f = v cc f 0.3 v reset = v cc f 0.3 v, wp /acc = v cc f 0.3 v 5 m a flash v cc standby current (reset ) i sb2 f v cc f = v cc f max, reset = v ss 0.3 v, wp /acc = v cc f 0.3 v 5 m a flash v cc current (automatic sleep mode) * 3 i sb3 f v cc f = v cc f max, ce f = v ss 0.3 v reset = v cc f 0.3 v, wp /acc = v cc f 0.3 v v in = v cc f 0.3 v or v ss 0.3 v 5 m a sram v cc standby current i sb1 s ce1 s > v cc s C 0.2 v, ce2s > v cc s C 0.2 v lb = ub > v cc sC0.2 v or < 0.2v 10 m a sram v cc standby current i sb2 s ce1 s > v cc s C 0.2 v or < 0.2v, ce2s < 0.2 v lb = ub > v cc sC0.2 v or < 0.2v 10 m a
mb84vd22184fm/vd22194fm -70 9 (continued) *1 : the i cc current listed includes both the dc operating current and the frequency dependent component. *2 : i cc active while embedded algorithm (program or erase) is in progress. *3 : automatic sleep mode enables the low power mode when address remain stable for 150 ns. *4 : applicable for only v cc f applying. *5 : embedded algorithm (program or erase) is in progress. (@5 mhz) *6 : v cc indicates lower of v cc f or v cc s. parameter symbol test conditions value unit min typ max input low level v il C0.30.5v input high level v ih 2.2 v cc +0.3* 6 v voltage for sector protection, and temporary sector unprotection (reset ) * 4 v id 11.5 12.5 v voltage for program acceleration (wp /acc) * 4 v acc 8.5 9.0 9.5 v sram output low level v ol v cc s = v cc s min, i ol = 0.1 ma 0.4 v sram output high level v oh v cc s = v cc s min, i oh = C0.1 ma 2.0 v flash output low level v ol v cc f = v cc f min, i ol = 4.0 ma 0.45 v flash output high level v oh v cc f = v cc f min, i oh = C0.1 ma v cc sC0.4 v flash low v cc f lock-out voltage v lko 2.3 2.5 v
mb84vd22184fm/vd22194fm -70 10 2. ac characteristics ?ce timing ? timing diagram for alternating sram to flash ? flash characteristics please refer to n 32m flash memory for mcp. ? sram characteristics, please refer to n 4m sram for mcp. parameter symbol test setup value unit jedec standard ce recover time t ccr min 0 ns ce f t ccr t ccr ce1 s ce2s t ccr t ccr
mb84vd22184fm/vd22194fm -70 11 n 32 m flash memory for mcp 1. flexible sector-erase architecture on flash memory ? eight 4 k words, and sixty three 32 k words. ? individual-sector, multiple-sector, or bulk-erase capability. 100000h (top boot block) sa39 : 64kb (32kw) sa40 : 64kb (32kw) sa41 : 64kb (32kw) sa42 : 64kb (32kw) sa43 : 64kb (32kw) sa44 : 64kb (32kw) sa45 : 64kb (32kw) sa46 : 64kb (32kw) sa47 : 64kb (32kw) sa48 : 64kb (32kw) sa49 : 64kb (32kw) sa50 : 64kb (32kw) sa51 : 64kb (32kw) sa52 : 64kb (32kw) sa53 : 64kb (32kw) sa54 : 64kb (32kw) sa55 : 64kb (32kw) sa56 : 64kb (32kw) sa57 : 64kb (32kw) sa58 : 64kb (32kw) sa59 : 64kb (32kw) sa60 : 64kb (32kw) sa61 : 64kb (32kw) sa62 : 64kb (32kw) sa63 : 8kb (4kw) sa64 : 8kb (4kw) sa65 : 8kb (4kw) sa66 : 8kb (4kw) sa67 : 8kb (4kw) sa68 : 8kb (4kw) 008000h 000000h 018000h 010000h 028000h 020000h 038000h 030000h 048000h 040000h 058000h 050000h 068000h 060000h 078000h 070000h 088000h 080000h 098000h 090000h 0a8000h 0a0000h 0b8000h 0b0000h 0c8000h 0c0000h 0d8000h 0d0000h 0e8000h 0e0000h 0f8000h 0f0000h sa0 : 64kb (32kw) sa1 : 64kb (32kw) sa2 : 64kb (32kw) sa3 : 64kb (32kw) sa4 : 64kb (32kw) sa5 : 64kb (32kw) sa6 : 64kb (32kw) sa7 : 64kb (32kw) sa8 : 64kb (32kw) sa9 : 64kb (32kw) sa10 : 64kb (32kw) sa11 : 64kb (32kw) sa12 : 64kb (32kw) sa13 : 64kb (32kw) sa14 : 64kb (32kw) sa15 : 64kb (32kw) sa16 : 64kb (32kw) sa17 : 64kb (32kw) sa18 : 64kb (32kw) sa19 : 64kb (32kw) sa20 : 64kb (32kw) sa21 : 64kb (32kw) sa22 : 64kb (32kw) sa23 : 64kb (32kw) sa24 : 64kb (32kw) sa25 : 64kb (32kw) sa26 : 64kb (32kw) sa27 : 64kb (32kw) sa28 : 64kb (32kw) sa29 : 64kb (32kw) sa30 : 64kb (32kw) sa31 : 64kb (32kw) sa32 : 64kb (32kw) sa33 : 64kb (32kw) sa34 : 64kb (32kw) sa35 : 64kb (32kw) sa36 : 64kb (32kw) sa37 : 64kb (32kw) sa38 : 64kb (32kw) sa69 : 8kb (4kw) sa70 : 8kb (4kw) bank a 108000h 118000h 110000h 128000h 120000h 138000h 130000h 148000h 140000h 158000h 150000h 168000h 160000h 178000h 188000h 180000h 198000h 190000h 1a8000h 1a0000h 1b8000h 1b0000h 1c8000h 1c0000h 1d8000h 1d0000h 1e8000h 1e0000h 1f8000h 1f0000h 1f9000h 1fffffh 1fa000h 1fb000h 1fc000h 1fd000h 1fe000h 1ff000h bank b 170000h (bottom boot block) 100000h sa39 : 64kb (32kw) sa40 : 64kb (32kw) sa41 : 64kb (32kw) sa42 : 64kb (32kw) sa43 : 64kb (32kw) sa44 : 64kb (32kw) sa45 : 64kb (32kw) sa46 : 64kb (32kw) sa47 : 64kb (32kw) sa48 : 64kb (32kw) sa49 : 64kb (32kw) sa50 : 64kb (32kw) sa51 : 64kb (32kw) sa52 : 64kb (32kw) sa53 : 64kb (32kw) sa54 : 64kb (32kw) sa55 : 64kb (32kw) sa56 : 64kb (32kw) sa57 : 64kb (32kw) sa58 : 64kb (32kw) sa59 : 64kb (32kw) sa60 : 64kb (32kw) sa61 : 64kb (32kw) sa62 : 64kb (32kw) sa63 : 64kb (32kw) sa64 : 64kb (32kw) sa65 : 64kb (32kw) sa66 : 64kb (32kw) sa67 : 64kb (32kw) sa68 : 64kb (32kw) 008000h 000000h 018000h 010000h 028000h 020000h 038000h 030000h 048000h 040000h 058000h 050000h 068000h 060000h 078000h 070000h 088000h 080000h 098000h 090000h 0a8000h 0a0000h 0b8000h 0b0000h 0c8000h 0c0000h 0d8000h 0d0000h 0e8000h 0e0000h 0f8000h 0f0000h sa0 : 8kb (4kw) sa1 : 8kb (4kw) sa2 : 8kb (4kw) sa3 : 8kb (4kw) sa4 : 8kb (4kw) sa5 : 8kb (4kw) sa6 : 8kb (4kw) sa7 : 8kb (4kw) sa8 : 64kb (32kw) sa9 : 64kb (32kw) sa10 : 64kb (32kw) sa11 : 64kb (32kw) sa12 : 64kb (32kw) sa13 : 64kb (32kw) sa14 : 64kb (32kw) sa15 : 64kb (32kw) sa16 : 64kb (32kw) sa17 : 64kb (32kw) sa18 : 64kb (32kw) sa19 : 64kb (32kw) sa20 : 64kb (32kw) sa21 : 64kb (32kw) sa22 : 64kb (32kw) sa23 : 64kb (32kw) sa24 : 64kb (32kw) sa25 : 64kb (32kw) sa26 : 64kb (32kw) sa27 : 64kb (32kw) sa28 : 64kb (32kw) sa29 : 64kb (32kw) sa30 : 64kb (32kw) sa31 : 64kb (32kw) sa32 : 64kb (32kw) sa33 : 64kb (32kw) sa34 : 64kb (32kw) sa35 : 64kb (32kw) sa36 : 64kb (32kw) sa37 : 64kb (32kw) sa38 : 64kb (32kw) sa69 : 64kb (32kw) sa70 : 64kb (32kw) 108000h 118000h 110000h 128000h 120000h 138000h 130000h 148000h 140000h 158000h 150000h 168000h 160000h 178000h 170000h 188000h 180000h 198000h 190000h 1a8000h 1a0000h 1b8000h 1b0000h 1c8000h 1c0000h 1d8000h 1d0000h 1e8000h 1e0000h 1f8000h 1f0000h 001000h 1fffffh 002000h 003000h 004000h 005000h 006000h 007000h bank a bank b
mb84vd22184fm/vd22194fm -70 12 sector address table (top boot type) (continued) b a n k sector sector address sector size (kwords) address range bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 b a n k b sa0 0 0 0 0 0 0 x x x x 32 000000h to 007fffh sa1 0 0 0 0 0 1 x x x x 32 008000h to 00ffffh sa2 0 0 0 0 1 0 x x x x 32 010000h to 017fffh sa3 0 0 0 0 1 1 x x x x 32 018000h to 01ffffh sa4 0 0 0 1 0 0 x x x x 32 020000h to 027fffh sa5 0 0 0 1 0 1 x x x x 32 028000h to 02ffffh sa6 0 0 0 1 1 0 x x x x 32 030000h to 037fffh sa7 0 0 0 1 1 1 x x x x 32 038000h to 03ffffh sa8 0 0 1 0 0 0 x x x x 32 040000h to 047fffh sa9 0 0 1 0 0 1 x x x x 32 048000h to 04ffffh sa10 0 0 1 0 1 0 x x x x 32 050000h to 057fffh sa11 0 0 1 0 1 1 x x x x 32 058000h to 05ffffh sa12 0 0 1 1 0 0 x x x x 32 060000h to 067fffh sa13 0 0 1 1 0 1 x x x x 32 068000h to 06ffffh sa14 0 0 1 1 1 0 x x x x 32 070000h to 077fffh sa15 0 0 1 1 1 1 x x x x 32 078000h to 07ffffh sa16 0 1 0 0 0 0 x x x x 32 080000h to 087fffh sa17 0 1 0 0 0 1 x x x x 32 088000h to 08ffffh sa18 0 1 0 0 1 0 x x x x 32 090000h to 097fffh sa19 0 1 0 0 1 1 x x x x 32 098000h to 09ffffh sa20 0 1 0 1 0 0 x x x x 32 0a0000h to 0a7fffh sa21 0 1 0 1 0 1 x x x x 32 0a8000h to 0affffh sa22 0 1 0 1 1 0 x x x x 32 0b0000h to 0b7fffh sa23 0 1 0 1 1 1 x x x x 32 0b8000h to 0bffffh sa24 0 1 1 0 0 0 x x x x 32 0c0000h to 0c7fffh sa25 0 1 1 0 0 1 x x x x 32 0c8000h to 0cffffh sa26 0 1 1 0 1 0 x x x x 32 0d0000h to 0d7fffh sa27 0 1 1 0 1 1 x x x x 32 0d8000h to 0dffffh sa28 0 1 1 1 0 0 x x x x 32 0e0000h to 0e7fffh sa29 0 1 1 1 0 1 x x x x 32 0e8000h to 0effffh sa30 0 1 1 1 1 0 x x x x 32 0f0000h to 0f7fffh sa31 0 1 1 1 1 1 x x x x 32 0f8000h to 0fffffh
mb84vd22184fm/vd22194fm -70 13 (continued) b a n k sector sector address sector size (kwords) address range bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 b a n k b sa32 1 0 0 0 0 0 x x x x 32 100000h to 107fffh sa33 1 0 0 0 0 1 x x x x 32 108000h to 10ffffh sa34 1 0 0 0 1 0 x x x x 32 110000h to 117fffh sa35 1 0 0 0 1 1 x x x x 32 118000h to 11ffffh sa36 1 0 0 1 0 0 x x x x 32 120000h to 127fffh sa37 1 0 0 1 0 1 x x x x 32 128000h to 12ffffh sa38 1 0 0 1 1 0 x x x x 32 130000h to 137fffh sa39 1 0 0 1 1 1 x x x x 32 138000h to 13ffffh sa40 1 0 1 0 0 0 x x x x 32 140000h to 147fffh sa41 1 0 1 0 0 1 x x x x 32 148000h to 14ffffh sa42 1 0 1 0 1 0 x x x x 32 150000h to 157fffh sa43 1 0 1 0 1 1 x x x x 32 158000h to 15ffffh sa44 1 0 1 1 0 0 x x x x 32 160000h to 167fffh sa45 1 0 1 1 0 1 x x x x 32 168000h to 16ffffh sa46 1 0 1 1 1 0 x x x x 32 170000h to 177fffh sa47 1 0 1 1 1 1 x x x x 32 178000h to 17ffffh b a n k a sa48 1 1 0 0 0 0 x x x x 32 180000h to 187fffh sa49 1 1 0 0 0 1 x x x x 32 188000h to 18ffffh sa50 1 1 0 0 1 0 x x x x 32 190000h to 197fffh sa51 1 1 0 0 1 1 x x x x 32 198000h to 19ffffh sa52 1 1 0 1 0 0 x x x x 32 1a0000h to 1a7fffh sa53 1 1 0 1 0 1 x x x x 32 1a8000h to 1affffh sa54 1 1 0 1 1 0 x x x x 32 1b0000h to 1b7fffh sa55 1 1 0 1 1 1 x x x x 32 1b8000h to 1bffffh sa56 1 1 1 0 0 0 x x x x 32 1c0000h to 1c7fffh sa57 1 1 1 0 0 1 x x x x 32 1c8000h to 1cffffh sa58 1 1 1 0 1 0 x x x x 32 1d0000h to 1d7fffh sa59 1 1 1 0 1 1 x x x x 32 1d8000h to 1dffffh sa60 1 1 1 1 0 0 x x x x 32 1e0000h to 1e7fffh sa61 1 1 1 1 0 1 x x x x 32 1e8000h to 1effffh sa62 1 1 1 1 1 0 x x x x 32 1f0000h to 1f7fffh sa63 1 1 1 1 1 1 0 0 0 x 4 1f8000h to 1f8fffh sa64 1 1 1 1 1 1 0 0 1 x 4 1f9000h to 1f9fffh sa65 1 1 1 1 1 1 0 1 0 x 4 1fa000h to 1fafffh sa66 1 1 1 1 1 1 0 1 1 x 4 1fb000h to 1fbfffh sa67 1 1 1 1 1 1 1 0 0 x 4 1fc000h to 1fcfffh sa68 1 1 1 1 1 1 1 0 1 x 4 1fd000h to 1fdfffh sa69 1 1 1 1 1 1 1 1 0 x 4 1fe000h to 1fefffh sa70 1 1 1 1 1 1 1 1 1 x 4 1ff000h to 1fffffh
mb84vd22184fm/vd22194fm -70 14 sector address table (bottom boot type) (continued) b a n k sector sector address sector size (kwords) address range bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 b a n k b sa70 1 1 1 1 1 1 x x x x 32 1f8000h to 1fffffh sa69 1 1 1 1 1 0 x x x x 32 1f0000h to 1f7fffh sa68 1 1 1 1 0 1 x x x x 32 1e8000h to 1effffh sa67 1 1 1 1 0 0 x x x x 32 1e0000h to 1e7fffh sa66 1 1 1 0 1 1 x x x x 32 1d8000h to 1dffffh sa65 1 1 1 0 1 0 x x x x 32 1d0000h to 1d7fffh sa64 1 1 1 0 0 1 x x x x 32 1c8000h to 1cffffh sa63 1 1 1 0 0 0 x x x x 32 1c0000h to 1c7fffh sa62 1 1 0 1 1 1 x x x x 32 1b8000h to 1bffffh sa61 1 1 0 1 1 0 x x x x 32 1b0000h to 1b7fffh sa60 1 1 0 1 0 1 x x x x 32 1a8000h to 1affffh sa59 1 1 0 1 0 0 x x x x 32 1a0000h to 1a7fffh sa58 1 1 0 0 1 1 x x x x 32 198000h to 19ffffh sa57 1 1 0 0 1 0 x x x x 32 190000h to 197fffh sa56 1 1 0 0 0 1 x x x x 32 188000h to 18ffffh sa55 1 1 0 0 0 0 x x x x 32 180000h to 187fffh sa54 1 0 1 1 1 1 x x x x 32 178000h to 17ffffh sa53 1 0 1 1 1 0 x x x x 32 170000h to 177fffh sa52 1 0 1 1 0 1 x x x x 32 168000h to 16ffffh sa51 1 0 1 1 0 0 x x x x 32 160000h to 167fffh sa50 1 0 1 0 1 1 x x x x 32 158000h to 15ffffh sa49 1 0 1 0 1 0 x x x x 32 150000h to 157fffh sa48 1 0 1 0 0 1 x x x x 32 148000h to 14ffffh sa47 1 0 1 0 0 0 x x x x 32 140000h to 147fffh sa46 1 0 0 1 1 1 x x x x 32 138000h to 13ffffh sa45 1 0 0 1 1 0 x x x x 32 130000h to 137fffh sa44 1 0 0 1 0 1 x x x x 32 128000h to 12ffffh sa43 1 0 0 1 0 0 x x x x 32 120000h to 127fffh sa42 1 0 0 0 1 1 x x x x 32 118000h to 11ffffh sa41 1 0 0 0 1 0 x x x x 32 110000h to 117fffh sa40 1 0 0 0 0 1 x x x x 32 108000h to 10ffffh sa39 1 0 0 0 0 0 x x x x 32 100000h to 107fffh
mb84vd22184fm/vd22194fm -70 15 b a n k sector sector address sector size (kwords) address range bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 b a n k b sa38 0 1 1 1 1 1 x x x x 32 0f8000h to 0fffffh sa37 0 1 1 1 1 0 x x x x 32 0f0000h to 0f7fffh sa36 0 1 1 1 0 1 x x x x 32 0e8000h to 0effffh sa35 0 1 1 1 0 0 x x x x 32 0e0000h to 0e7fffh sa34 0 1 1 0 1 1 x x x x 32 0d8000h to 0dffffh sa33 0 1 1 0 1 0 x x x x 32 0d0000h to 0d7fffh sa32 0 1 1 0 0 1 x x x x 32 0c8000h to 0cffffh sa31 0 1 1 0 0 0 x x x x 32 0c0000h to 0c7fffh sa30 0 1 0 1 1 1 x x x x 32 0b8000h to 0bffffh sa29 0 1 0 1 1 0 x x x x 32 0b0000h to 0b7fffh sa28 0 1 0 1 0 1 x x x x 32 0a8000h to 0affffh sa27 0 1 0 1 0 0 x x x x 32 0a0000h to 0a7fffh sa26 0 1 0 0 1 1 x x x x 32 098000h to 09ffffh sa25 0 1 0 0 1 0 x x x x 32 090000h to 097fffh sa24 0 1 0 0 0 1 x x x x 32 088000h to 08ffffh sa23 0 1 0 0 0 0 x x x x 32 080000h to 087fffh b a n k a sa22 0 0 1 1 1 1 x x x x 32 078000h to 07ffffh sa21 0 0 1 1 1 0 x x x x 32 070000h to 077fffh sa20 0 0 1 1 0 1 x x x x 32 068000h to 06ffffh sa19 0 0 1 1 0 0 x x x x 32 060000h to 067fffh sa18 0 0 1 0 1 1 x x x x 32 058000h to 05ffffh sa17 0 0 1 0 1 0 x x x x 32 050000h to 057fffh sa16 0 0 1 0 0 1 x x x x 32 048000h to 04ffffh sa15 0 0 1 0 0 0 x x x x 32 040000h to 047fffh sa14 0 0 0 1 1 1 x x x x 32 038000h to 03ffffh sa13 0 0 0 1 1 0 x x x x 32 030000h to 037fffh sa12 0 0 0 1 0 1 x x x x 32 028000h to 02ffffh sa11 0 0 0 1 0 0 x x x x 32 020000h to 027fffh sa10 0 0 0 0 1 1 x x x x 32 018000h to 01ffffh sa9 0 0 0 0 1 0 x x x x 32 010000h to 017fffh sa8 0 0 0 0 0 1 x x x x 32 008000h to 00ffffh sa7 0 0 0 0 0 0 1 1 1 x 4 007000h to 007fffh sa6 0 0 0 0 0 0 1 1 0 x 4 006000h to 006fffh sa5 0 0 0 0 0 0 1 0 1 x 4 005000h to 005fffh sa4 0 0 0 0 0 0 1 0 0 x 4 004000h to 004fffh sa3 0 0 0 0 0 0 0 1 1 x 4 003000h to 003fffh sa2 0 0 0 0 0 0 0 1 0 x 4 002000h to 002fffh sa1 0 0 0 0 0 0 0 0 1 x 4 001000h to 001fffh sa0 0 0 0 0 0 0 0 0 0 x 4 000000h to 000fffh
mb84vd22184fm/vd22194fm -70 16 sector group addresses table (top boot type) sector group a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 000000xxx sa0 sga1 0000 01 xxx sa1 to sa3 10 11 sga2 0 0 0 1xxxxx sa4 to sa7 sga3 0 0 1 0xxxxxsa8 to sa11 sga4 0 0 1 1xxxxxsa12 to sa15 sga5 0 1 0 0xxxxxsa16 to sa19 sga6 0 1 0 1xxxxxsa20 to sa23 sga7 0 1 1 0xxxxxsa24 to sa27 sga8 0 1 1 1xxxxxsa28 to sa31 sga9 1 0 0 0xxxxxsa32 to sa35 sga10 1 0 0 1xxxxxsa36 to sa39 sga11 1 0 1 0xxxxxsa40 to sa43 sga12 1 0 1 1xxxxxsa44 to sa47 sga13 1 1 0 0xxxxxsa48 to sa51 sga14 1 1 0 1xxxxxsa52 to sa55 sga15 1 1 1 0xxxxxsa56 to sa59 sga16 1 1 1 1 00 x x x sa60 to sa62 01 10 sga17 111111000 sa63 sga18 111111001 sa64 sga19 111111010 sa65 sga20 111111011 sa66 sga21 111111100 sa67 sga22 111111101 sa68 sga23 111111110 sa69 sga24 111111111 sa70
mb84vd22184fm/vd22194fm -70 17 sector group addresses table (bottom boot type) sector group a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 000000000 sa0 sga1 000000001 sa1 sga2 000000010 sa2 sga3 000000011 sa3 sga4 000000100 sa4 sga5 000000101 sa5 sga6 000000110 sa6 sga7 000000111 sa7 sga8 0000 01 x x x sa8 to sa10 10 11 sga9 0 0 0 1xxxxxsa11 to sa14 sga10 0 0 1 0xxxxxsa15 to sa18 sga11 0 0 1 1xxxxxsa19 to sa22 sga12 0 1 0 0xxxxxsa23 to sa26 sga13 0 1 0 1xxxxxsa27 to sa30 sga14 0 1 1 0xxxxxsa31 to sa34 sga15 0 1 1 1xxxxxsa35 to sa38 sga16 1 0 0 0xxxxxsa39 to sa42 sga17 1 0 0 1xxxxxsa43 to sa46 sga18 1 0 1 0xxxxxsa47 to sa50 sga19 1 0 1 1xxxxxsa51 to sa54 sga20 1 1 0 0xxxxxsa55 to sa58 sga21 1 1 0 1xxxxxsa59 to sa62 sga22 1 1 1 0xxxxxsa63 to sa66 sga23 1 1 1 1 00 x x x sa67 to sa69 01 10 sga24 111111xxx sa70
mb84vd22184fm/vd22194fm -70 18 sector group protection verify autoselect codes table (top boot type) legend: l = v il , h = v ih . see dc characteristics for voltage levels. * : outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. expanded autoselect code table (top boot type) sector group protection verify autoselect codes table (bottom boot type) legend: l = v il , h = v ih . see dc characteristics for voltage levels. * : outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. expanded autoselect code table (bottom boot type) type a 20 to a 12 a 6 a 3 a 2 a 1 a 0 code (hex) manufactures code ba l l l l l 04h device code ba l l l l h 2250h sector group protection sa l l l h l 01h* type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufactures code 04h0000000000000100 device code 2250h 0 0 10001001010000 sector group protection 01h0000000000000001 type a 20 to a 12 a 6 a 3 a 2 a 1 a 0 code (hex) manufactures code ba l l l l l 04h device code ba l l l l h 2253h sector group protection sa l l l h l 01h* type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufactures code 04h0000000000000100 device code 2253h0010001001010011 sector group protection 01h0000000000000001
mb84vd22184fm/vd22194fm -70 19 command definitions table (continued) command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cy- cle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset* 1 1 xxxh f0h ? ? ? ??????? read/reset* 1 3 555h aah 2aah 55h 555h f0h ra rd ???? autoselect 3 555h aah 2aah 55h (ba) 555h 90h ?????? program 4 555h aah 2aah 55h 555h a0h pa pd ???? program suspend 1bab0h ? ? ? ??????? program resume 1ba30h ? ? ? ??????? chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h erase suspend 1 ba b0h ? ? ? ??????? erase resume 1 ba 30h ? ? ? ??????? set to fast mode 3 555h aah 2aah 55h 555h 20h ?????? fast program * 2 2 xxxh a0h pa pd ? ??????? reset from fast mode * 2 2 ba 90h xxxh f0h* 6 ? ??????? extended sector group protection * 3 4 xxxh 60h spa 60h spa 40h spa sd ???? query * 4 1 (ba) 55h 98h ? ? ? ??????? hiddenrom entry 3 555h aah 2aah 55h 555h 88h ?????? hiddenrom program * 5 4 555h aah 2aah 55h 555h a0h (hra) pa pd ???? hiddenrom exit * 5 4 555h aah 2aah 55h (hrba) 555h 90h xxxh 00h ????
mb84vd22184fm/vd22194fm -70 20 (continued) *1 : both of these reset commands are equivalent. *2 : this command is valid during fast mode. *3 : this command is valid while reset = v id . *4 : the valid address are a 6 to a 0 . *5 : this command is valid during hiddenrom mode. *6 : the date 00h is also acceptable. notes: address bits a 20 to a 11 = x = h or l for all address commands except or program address (pa) , sector address (sa) , bank address (ba) . bus operations are defined in user bus operations tables ( n device bus operation). ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. ba = bank address (a 20 to a 18 ) rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of write pulse. spa = sector group address to be protected. set sector group address and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) . sd = sector group protection verify data. output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. hra = address of the hiddenrom area top boot type : 1ff000h to 1ff07fh bottom boot type : 000000h to 00007fh hrba = bank address of the hiddenrom area top boot type : a 20 = a 19 = a 18 = 1 bottom boot type : a 20 = a 19 = a 18 = 0 the system should generate the following address patterns : word mode : 555h or 2aah to addresses a 10 to a 0 both read/reset commands are functionally equivalent, resetting the device to the read mode. the command combinations not described in command definitions table are illegal.
mb84vd22184fm/vd22194fm -70 21 2. ac characteristics ? read only operations characteristics * : test conditions: output load:1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to 3.0 v timing measurement reference level input: 0.5 vccf output: 0.5 vccf parameter symbol test setup value* unit jedec standard min max read cycle time t avav t rc 70 ? ns address to output delay t avqv t acc ce f = v il oe = v il ? 70 ns chip enable to output delay t elqv t ce oe = v il ? 70 ns output enable to output delay t glqv t oe ? 30 ns chip enable to output high-z t ehqz t df ? 25 ns output enable to output high-z t ghqz t df ? 25 ns output hold time from addresses, ce f or oe , whichever occurs first t axqx t oh 0 ? ns reset pin low to read mode t ready ? 20 m s
mb84vd22184fm/vd22194fm -70 22 ? write/erase/program operations *1 : this does not include the preprogramming time. *2 : this timing is for sector group protection operation. parameter symbol value unit jedec standard min typ max write cycle time t avav t wc 70 ?? ns address setup time t avwl t as 0 ?? ns address setup time to oe low during toggle bit polling t aso 12 ?? ns address hold time t wlax t ah 45 ?? ns address hold time from ce f or oe high during toggle bit polling t aht 0 ?? ns data setup time t dvwh t ds 30 ?? ns data hold time t whdx t dh 0 ?? ns output enable hold time read t oeh 0 ?? ns toggle and data polling 10 ?? ns ce f high during toggle bit polling t ceph 20 ?? ns oe high during toggle bit polling t oeph 20 ?? ns read recover time before write t ghwl t ghwl 0 ?? ns read recover time before write t ghel t ghel 0 ?? ns ce f setup time t elwl t cs 0 ?? ns we setup time t wlel t ws 0 ?? ns ce f hold time t wheh t ch 0 ?? ns we hold time t ehwh t wh 0 ?? ns write pulse width t wlwh t wp 35 ?? ns ce f pulse width t eleh t cp 35 ?? ns write pulse width high t whwl t wph 25 ?? ns ce f pulse width high t ehel t cph 25 ?? ns sector erase operation * 1 t whwh2 t whwh2 ? 0.5 ? s v cc f setup time t vcs 50 ?? s rise time to v id * 2 t vidr 500 ?? ns rise time to v id * 2 t vaccr 500 ?? ns voltage transition time * 2 t vlht 4 ?? s write pulse width * 2 t wpp 100 ?? s oe setup time to we active * 2 t oesp 4 ?? s ce f setup time to we active * 2 t csp 4 ?? s recover time from ry/by t rb ??? ns reset pulse width t rp 500 ?? ns reset high level period before read t rh 200 ?? ns program/erase valid to ry/by delay t busy ?? 90 ns delay time from embedded output enable t eoe ?? 70 ns erase time-out time t tow 50 ?? s erase suspend transition time t spd ??? s
mb84vd22184fm/vd22194fm -70 23 ? read cycle (flash) we oe ce f t cef t oe dq address stable high-z output valid high-z t oeh t acc t rc reset t acc t oh dq t rc address stable high-z output valid t rh t df address address t rh t cef t rp ce f
mb84vd22184fm/vd22194fm -70 24 ? write cycle (we control) (flash) t ch t wp t whwh1 t wc t ah ce f oe t rc dq t as t oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t cef t ds d out address notes : pa is address of the memory location to be programmed. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence. these waveforms are for the 16 mode.
mb84vd22184fm/vd22194fm -70 25 ? write cycle (ce f control) (flash) notes : pa is address of the memory location to be programmed. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence. these waveforms are for the 16 mode. t cp t ds t whwh1 t wc t ah we oe dq t as t cph t dh dq 7 a0h d out ce f 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd address
mb84vd22184fm/vd22194fm -70 26 ? ac waveforms chip/sector erase operations (flash) address v cc f ce f oe dq we 555h 2aah 555h 555h 2aah sa* t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc t wp aah 55h 80h aah 55h 10h/ 30h for sector erase 30h * : sa is the sector address for sector erase. addresses = 555h for chip erase. note : these waveform are for the 16 mode.
mb84vd22184fm/vd22194fm -70 27 ? ac waveforms for data polling during embedded algorithm operations (flash) * : dq 7 = valid data (the device has completed the embedded operation.) t oeh t oe t whwh1 or 2 ce f oe we dq 7 t df t ch t cef dq 7 = valid data dq 7 * dq dq 6 to dq 0 = output flag t eoe dq 8 to dq 0 valid data high-z high-z (dq 6 to dq 0 ) data input data input t busy ry/by
mb84vd22184fm/vd22194fm -70 28 ? ac waveforms for toggle bit during embedded algorithm operations (flash) * : dq 6 stops toggling (the device has completed the embedded operation). address ry/by ce f we dq 6 /dq 2 oe t as t busy toggle t aht t aht t aso t oeh t oeh t oe data toggle data toggle data stop toggling data t cef * output valid t dh t ceph t oeph
mb84vd22184fm/vd22194fm -70 29 ? back-to-back read/write timing diagram (flash) note : this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1: address of bank 1. ba2: address of bank 2. cef dq we address ba1 ba1 ba1 ba2 (555h) ba2 (pa) ba2 (pa) oe valid output valid output valid output status valid intput valid intput t rc t rc t rc t rc t wc t wc t aht t as t as t ah t acc t ce t oe t oeh t wp t ghwl t ds t df t dh t df t ceph read command command read read read (a0h) (pd)
mb84vd22184fm/vd22194fm -70 30 ?ry/by timing diagram during write/erase operations (flash) ? reset , ry/by timing diagram (flash) rising edge of the last write pulse ce f ry/by we t busy entire programming or erase operations t rp reset t ready ry/by we t rb
mb84vd22184fm/vd22194fm -70 31 ? temporary sector unprotection (flash) v cc f v id reset 3v ce f we ry/by program or erase command sequence t vidr t vlht t vcs t vlht t vlht unprotection period 3v
mb84vd22184fm/vd22194fm -70 32 ? extended sector group protection (flash) sgax : sector group address to be protected sgay : next group sector address to be protected time-out : time-out window = 250 m s (min) sgay reset a 6 oe we ce f data a 1 v cc f a 0 address sgax sgax 60h 01h 40h 60h 60h time-out t vcs t vlht t vidr t oe t wp t wc t wc
mb84vd22184fm/vd22194fm -70 33 ? accelerated program (flash) 3 v wp/acc v cc f cef we ry/by t vlht program command sequence 3 v t vlht t vcs t vaccr v acc t vlht acceleration period
mb84vd22184fm/vd22194fm -70 34 3. erase and programming performance parameter limits unit comments min typ max sector erase time ? 0.5 2.0 s excludes programming time prior to erasure word programming time ? 6.0 100 m s excludes system-level overhead chip programming time ? 12.6 50 s excludes system-level overhead program/erase cycle 100,000 ?? cycle ?
mb84vd22184fm/vd22194fm -70 35 n 4 m sram for mcp 1. ac characteristics ?read cycle (sram) note: test conditionsC output load:1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to v cc s timing measurement reference level input: 0.5v cc s output: 0.5v cc s parameter symbol value unit min max read cycle time t rc 70 ns address access time t aa 70ns chip enable (ce1 s) access time t co1 70ns chip enable (ce2s) access time t co2 70ns output enable access time t oe 35ns lb , ub to output valid t ba 70ns chip enable (ce1 s low and ce2s high) to output active t coe 5ns output enable low to output active t oee 0ns ub , lb enable low to output active t be 0ns chip enable (ce1 s high or ce2s low) to output high-z t od 25ns output enable high to output high-z t odo 25ns ub , lb output enable to output high-z t bd 25ns output data hold time t oh 10 ns
mb84vd22184fm/vd22194fm -70 36 ?read cycle (sram) note: we remains high for the read cycle. t rc t aa t oh t co1 t od t odo t oee t coe valid data output address ce1 s oe dq ce2s t coe t oe t co2 t od lb , ub t ba t bd t be
mb84vd22184fm/vd22194fm -70 37 ? write cycle (sram) parameter symbol value unit min max write cycle time t wc 70 ns write pulse width t wp 50 ns chip enable to end of write t cw 55 ns address valid to end of write t aw 55 ns ub , lb to end of write t bw 55 ns address setup time t as 0ns write recovery time t wr 0ns we low to output high-z t odw 25 ns we high to output active t oew 0ns data setup time t ds 30 ns data hold time t dh 0ns
mb84vd22184fm/vd22194fm -70 38 ?write cycle * 1 (we control) (sram) t wc t as t wp t wr t cw t odw t oew t ds t dh valid data input address we ce1 s d out d in ce2s t cw *2 *4 *3 *4 t bw lb , ub t aw *1 : if oe is high during the write cycle, the outputs will remain at high impedance. *2 : if ce1 s goes low (or ce2s goes high) coincident with or after we goes low, the output will remain at high impedance. *3 : if ce1 s goes high (or ce2s goes low) coincident with or before we goes high, the output will remain at high impedance. *4 : because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied.
mb84vd22184fm/vd22194fm -70 39 ?write cycle * 1 (ce1 s control) (sram) *1 : if oe is high during the write cycle, the outputs will remain at high impedance. *2 : because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. t wc t as t wp t wr t cw t odw t coe t ds t dh valid data input address we ce1 s d out d in ce2s t cw *2 *2 lb , ub t bw t be t aw
mb84vd22184fm/vd22194fm -70 40 ?write cycle * 1 (ce2s control) (sram) *1 : if oe is high during the write cycle, the outputs will remain at high impedance. *2 : because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. t wc t as t wp t wr t cw t odw t coe t ds t dh valid data input address we ce1 s d out d in ce2s *2 *2 t cw lb , ub t bw t be t aw
mb84vd22184fm/vd22194fm -70 41 ?write cycle * 1 (lb , ub control) (sram) *1 : if oe is high during the write cycle, the outputs will remain at high impedance. *2 : because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. t wc t ds t dh address lb , ub we d in t wp ce2s t cw ce1 s t as t wr t bw t odw t coe d out t be valid data input *2 *2 t cw t aw
mb84vd22184fm/vd22194fm -70 42 2. data retention characteristics (sram) note : t rc : read cycle time ?ce1 s controlled data retention mode * 1 *1 : in ce1 s controlled data retention mode, input level of ce2s should be fixed vccs to vccsC0.2 v or vss to 0.2 v during data retention mode. other input and input/output pins can be used between C0.3 v to vccs+0.3 v. *2 : when ce1 s is operating at the v ih min level, the standby current is given by i sb1 s during the transition of v cc s from v cc s max to v ih min level. ? ce2s controlled data retention mode * * : in ce2s controlled data retention mode, input and input/output pins can be used between C0.3 v to vccs+0.3v. parameter symbol value unit min typ max data retention supply voltage v dh 1.5 3.1 v standby current v dh = 3.0 v i dds2 10 m a chip deselect to data retention mode time t cdr 0ns recovery time t r t rc ns v cc s 2.7 v v ih gnd data retention mode *2 t cdr ce1 s v cc s C 0.2 v *2 t r v dh v cc s 2.7 v gnd data retention mode v ih v il ce2s t cdr t r 0.2 v v dh
mb84vd22184fm/vd22194fm -70 43 n pin capacitance note : test conditions t a = + 25c, f = 1.0 mhz n handling of package please handle this package carefully since the sides of package create acute angles. n caution the high voltage (v id ) cannot apply to address pins and control pins except reset . exception is when autoselect and sector group protect function are used, then the high voltage (v id ) can be applied to reset . without the high voltage (v id ) , sector group protection can be achieved by using extended sector group protection command. parameter symbol test setup value unit typ max input capacitance c in v in = 0 11 14 pf output capacitance c out v out = 0 12 16 pf control pin capacitance c in2 v in = 0 14 16 pf wp /acc pin capacitance c in3 v in = 0 21.5 26 pf
mb84vd22184fm/vd22194fm -70 44 n ordering information mb84vd2218 4 fm -70 pbs device number/description 32mega-bit (2m 16-bit) dual operation flash memory 3.0 v-only read, program, and erase 4mega-bit (256k 16-bit) sram boot code sector architecture 84vd2218 = top sector 84vd2219 = bottom sector pa c k a g e t y p e pbs = 56-ball fbga speed option see product selector guide device revision bank architecture 4 = 8mbit / 24mbit (fixed bank)
mb84vd22184fm/vd22194fm -70 45 n package dimension 56-ball plastic fbga (bga-56p-m03) dimensions in mm (inches) note: the values in parentheses are reference values. c 2002 fujitsu limited bga560030sc-1-1 9.000.10(.354.004) 7.000.10 (.276.004) index-mark area 0.10(.004) 0.300.10 (.012.004) (stand off) max. 1.2(.047) (mounting height) 0.80 (.031) 5.60(.220) 0.80 (.031) 5.60(.220) a b c d e f g h j k 1 2 3 4 5 6 7 8 56-?.018 C.002 +.004 C0.05 +0.10 56-?0.45 m 0.08(.003)
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